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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chih-Chyau Yang Hui-Ming Lin Shih-Lun Chen Tien-Ching Wang Jun-Jie Zhu Chien-Ming Wu Chun-Ming Huang Chin-Long Wey |
| Copyright Year | 2011 |
| Description | Author affiliation: National Chip Implementation Center (CIC), Hsinchu, Taiwan (Chih-Chyau Yang; Hui-Ming Lin; Shih-Lun Chen; Tien-Ching Wang; Jun-Jie Zhu; Chien-Ming Wu; Chun-Ming Huang; Chin-Long Wey) |
| Abstract | This paper presents a configurable CONCORD platform for Multi-Project System-on-a-Chip (MP-SoC) implementation. The multi-projects platform was created for integrating heterogeneous SoC projects into a single chip. The total silicon prototyping cost for these projects can be greatly reduced by sharing the common SoC platform. A configurable SoC prototyping platform CONCORD is created as a verification platform for emulating the hardware of MP-SoC before chip being taped out. The CONCORD system provides higher connection flexibility, modularization, and architecture consistence than conventional FPGA systems. To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented with eleven SoC projects sharing the common platform. The experimental results show that 91.42 $mm^{2}$ silicon areas reduced by the MP-SoC methodology. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 382197 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424485000 |
| e-ISBN | 9781424484997 |
| DOI | 10.1109/VDAT.2011.5783593 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-04-25 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | System-on-a-chip Silicon Hardware Field programmable gate arrays Pins IP networks CONCORD Multi-Project SoC Silicon Prototyping |
| Content Type | Text |
| Resource Type | Article |
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