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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sungjae Kim Shragowitz, E. Karypis, G. Rung-Bin Lin |
| Copyright Year | 2007 |
| Description | Author affiliation: Univ. of Minnesota, Minneapolis (Sungjae Kim; Shragowitz, E.; Karypis, G.) |
| Abstract | This paper presents a fast fixed-die standard cell placement algorithm. Placement is achieved by a combination of top-down partitioning with the incremental row-by-row construction. This paper concentrates on the construction part of this process. Gate sizing is interleaved with the placement construction process. Before placement, every gate is given its minimal size. During the placement, gates are resized to satisfy the timing constraints. Behavior of the placement is adapted based on dynamically recomputed net delay bounds. Experimental results show significant improvement in timing, predictability of results, and run time with respect to a commercial placement tool. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 3534878 |
| Page Count | 4 |
| File Format | |
| ISBN | 1424405823 |
| DOI | 10.1109/VDAT.2007.373225 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-04-25 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Interleaved codes Timing Energy consumption Computer science Partitioning algorithms Delay effects Switching circuits Finishing Routing Algorithm design and analysis |
| Content Type | Text |
| Resource Type | Article |
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