NDLI: Testing Crosstalk Faults of Data and Address Buses in Embedded RAMs

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Testing Crosstalk Faults of Data and Address Buses in Embedded RAMs

Content Provider	IEEE Xplore Digital Library
Author	Jiunn-Der Yu Jin-Fu Li Tsu-Wei Tseng
Copyright Year	2007
Description	Author affiliation: Nat. Central Univ., Jhongli (Jiunn-Der Yu; Jin-Fu Li; Tsu-Wei Tseng)
Abstract	Random access memories (RAMs) have many long parallel wires which incur a greater probability for excessive crosstalk coupling effect. This paper presents a test algorithm for detecting crosstalk faults of address and data buses in RAMs. The test algorithm requires 12n+2m+2 Read/Write operations to cover 100% crosstalk faults for a RAM with m-bit addresses, n-bit data inputs/outputs. A BIST supporting March-CW and the proposed test is also implemented. Experimental results show that the area cost of the BIST is only about 3.1% for an 8 Ktimes16-bit RAM based on TSMC 0.18 mum standard cell library.
Starting Page	1
Ending Page	4
File Size	2570072
Page Count	4
File Format	PDF
ISBN	1424405823
DOI	10.1109/VDAT.2007.373218
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-25
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Crosstalk Circuit faults Data buses Integrated circuit interconnections Delay Read-write memory Built-in self-test Fault detection Capacitance
Content Type	Text
Resource Type	Article

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