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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ullah, Z. Jaiswal, M.K. Cheung, R.C.C. |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Electron. Eng., City Univ. of Hong Kong, Kowloon Tong, China (Ullah, Z.; Jaiswal, M.K.; Cheung, R.C.C.) |
| Abstract | Even though, TCAM provides search operation in a constant time, when compared with Static Random Access Memories (SRAMs), TCAMs have certain limitations such as low storage density, relatively slow access time, low scalability, complex circuitry, and expensive costs. Hence, the need for a TCAM architecture arises that can use SRAM (with additional logic) to behave like TCAM. This paper presents the idea of Hybrid-Partitioned, SRAM-based architecture (HP-TCAM), which provides the same functionality as TCAM. We implemented and analyzed an example design of 512 × 36 HP-TCAM on Xilinx FPGAs with its different design parameters. Energy/bit/search, as an important metric, for the design is 47.13 fJ on Virtex-7 FPGA. Furthermore, we have provided in detail, all the implementation results and power consumption for our designs. |
| Sponsorship | Circuits Syst. Soc. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 111150 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479900046 |
| DOI | 10.1109/FPL.2013.6645583 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-09-02 |
| Publisher Place | Portugal |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays Random access memory Computer aided manufacturing Clocks Partitioning algorithms Power demand Computer architecture |
| Content Type | Text |
| Resource Type | Article |
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