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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chin Hau Hoo Yajun Ha Kumar, A. |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore, Singapore (Chin Hau Hoo; Yajun Ha; Kumar, A.) |
| Abstract | Leakage power has become an important component of the total power consumption in FPGAs as process technology shrinks. In addition, a significant amount of leakage power in FPGAs is consumed by the routing resources. Therefore, leakage power reduction in FPGAs should begin with the routing resources. In this paper, we propose a novel directional coarse-grained power gating architecture for switch boxes. In addition, the existing VPR routing algorithm has been adapted with a new cost function to support the new power gating architecture. Results have shown that the new cost function yields an average improvement of 22% as compared to the existing VPR cost function in terms of the number of power gating regions that can be turned off. |
| Sponsorship | Circuits Syst. Soc. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 222255 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479900046 |
| DOI | 10.1109/FPL.2013.6645548 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-09-02 |
| Publisher Place | Portugal |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Routing Field programmable gate arrays Switches Switching circuits Logic gates Transistors Cost function power-aware routing algorithm Coarse-grained power gating |
| Content Type | Text |
| Resource Type | Article |
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