NDLI: On the difficulty of pin-to-wire routing in FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Shah, N. Rose, J.
Copyright Year	2012
Description	Author affiliation: The Edwards S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Canada (Shah, N.; Rose, J.)
Abstract	While FPGA programmable routing networks are designed to connect logic block output pins to input pins, FPGA users and architects sometimes become motivated to create connections between pins and specific wires in an FPGA. We call these pin-to-wire connections, and they are motivated by several reasons: first, a desire to employ routing-by-abutment, as commonly done in custom VLSI, to build modular, pre-laid out systems. Second, partial reconfiguration of FPGAs often requires that circuits in the FPGA connect by abutment. Third, pin-to-wire routing is required to make use of resources that reside within the routing network itself, such as the plentiful multiplexers in the network, or even the configuration bits themselves. In this paper we attempt to understand and measure how difficult it is to form such pin-to-wire connections. We show, for example, under an experimental scenario close to routing-by-abutment, that the total routed wirelength compared to a flat placement of the complete system increases by about 6%, that the critical path delay increases by 15% and the router effort goes up by a factor of 3.5. To achieve this result, it is important to be careful in selecting the specific target wires. Overall we demonstrate that while pin-to-wire connections definitely impose increased stress on the routing architecture and router, it is possible to route some reasonable number of them, and so they can be used under some circumstances.
Starting Page	83
Ending Page	90
File Size	1108385
Page Count	8
File Format	PDF
ISBN	9781467322577
e-ISBN	9781467322560
e-ISBN	9781467322553
DOI	10.1109/FPL.2012.6339245
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-29
Publisher Place	Norway
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Wires Field programmable gate arrays Pins Multiplexing Delay Table lookup
Content Type	Text
Resource Type	Article

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