NDLI: High-level aging estimation for FPGA-mapped designs

Content Provider	IEEE Xplore Digital Library
Author	Amouri, A. Tahoori, M.
Copyright Year	2012
Description	Author affiliation: Dependable Nano Computing, Karlsruhe Institute of Technology (KIT), Haid-und-Neu-Str. 7, 76131, Germany (Amouri, A.; Tahoori, M.)
Abstract	As the state-of-the-art FPGA devices use the latest advancements in CMOS technology, they also face the reliability challenges of nano-scale CMOS. Transistor aging, mainly due to Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI), is a major reliability issue. In this paper, we present a tool to predict the amount of aging-induced degradation for designs mapped to FPGA devices, to help the designers, in an early phase of the design flow, to choose the appropriate mapping and/or optimization efforts, in order to prolong the lifetime of their FPGA-mapped designs. The tool is based on system level abstractions for both BTI and HCI device level models, in addition to implicit device-level information existed in the power and timing reports provided from the FPGA's vendor tools. A case study of using the tool to explore different designs and mapping options shows that aging of the FPGA device is dependent on the design loaded onto it. Furthermore, different mappings and optimizations of the same circuit can result in different aging rates.
Starting Page	284
Ending Page	291
File Size	1066860
Page Count	8
File Format	PDF
ISBN	9781467322577
e-ISBN	9781467322560
e-ISBN	9781467322553
DOI	10.1109/FPL.2012.6339194
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-08-29
Publisher Place	Norway
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Aging Estimation Delay Integrated circuit modeling Transistors Human computer interaction
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Accurate Thermal-Profile Estimation and Validation for FPGA-Mapped Circuits

Survey of FPGA low power design

High-Level Power Estimation Model for SOC with FPGA Prototyping

Activity Estimation for Field-Programmable Gate Arrays

An accurate dynamic power model on FPGA routing resources

Edge-map: Optimal Performance Driven Technology Mapping for Iterative Lut Based Fpga Designs

FPGA interconnect design using logical effort

High-Level FPGA Programming through Mapping Process Networks to FPGA Resources

Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs

High-level aging estimation for FPGA-mapped designs

Similar Documents

Accurate Thermal-Profile Estimation and Validation for FPGA-Mapped Circuits

Survey of FPGA low power design

High-Level Power Estimation Model for SOC with FPGA Prototyping

Activity Estimation for Field-Programmable Gate Arrays

An accurate dynamic power model on FPGA routing resources

Edge-map: Optimal Performance Driven Technology Mapping for Iterative Lut Based Fpga Designs

FPGA interconnect design using logical effort

High-Level FPGA Programming through Mapping Process Networks to FPGA Resources

Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs

High-level aging estimation for FPGA-mapped designs