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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Roca, A. Flich, J. Dimitrakopoulos, G. |
| Copyright Year | 2012 |
| Description | Author affiliation: Parallel Architectures Lab (GAP), Universitat Politècnica de València, Spain (Roca, A.; Flich, J.) || Electrical and Computer Engineering Dept., Democritus University of Thrace, Greece (Dimitrakopoulos, G.) |
| Abstract | Networks-on-FPGA consist of a network of switches connected with point-to-point links and can cover sufficiently the communication needs of complex systems implemented on FPGA platforms. The efficient implementation of such networks requires the appropriate tuning of their components to the characteristics of the FPGA's logic and memory resources. In this paper, we present a distributed switch architecture that exploits in the best way the structure of the FPGA and achieves significant area/delay savings when compared to baseline switch architectures; more than 50% increase in operating frequency is achieved for similar area. The proposed switch operates as an elastic pipeline and can be spread throughout the FPGA chip irrespective the topology of the network and without limiting the placement options of the corresponding EDA tools. |
| Starting Page | 394 |
| Ending Page | 399 |
| File Size | 592114 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467322577 |
| e-ISBN | 9781467322560 |
| e-ISBN | 9781467322553 |
| DOI | 10.1109/FPL.2012.6339135 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-08-29 |
| Publisher Place | Norway |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Switches Field programmable gate arrays Delay Random access memory Pipelines Multiplexing Organizations |
| Content Type | Text |
| Resource Type | Article |
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