NDLI: Field Programmable Gate Array Implementation of Parts-Based Object Detection for Real Time Video Applications

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2015 25th International Conference on Field Programmable Logic and Applications (FPL)

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

2013 23rd International Conference on Field programmable Logic and Applications

22nd International Conference on Field Programmable Logic and Applications (FPL)

2011 21st International Conference on Field Programmable Logic and Applications

2010 International Conference on Field Programmable Logic and Applications

Table of Contents

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An FPGA-based Transverse Multibunch Feedback System for Diamond Light Source

Control Techniques for Coupling a Coarse-Grain Reconfigurable Array with a Generic RISC Core

Exploiting Dynamic Reconfiguration for FPGA Based Network Intrusion Detection Systems

A Scalable, High-Performance Motion Estimation Application for a Weakly-Programmable FPGA Architecture

Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic

An FPGA Based Hybrid Processor Emulation Platform

Parallelizing Simulated Annealing-Based Placement Using GPGPU

Efficiently Generating FPGA Configurations through a Stack Machine

Optimization of Regular Expression Pattern Matching Circuit Using At-Most Two-Hot Encoding on FPGA

A Reconfigurable System Based on a Parallel and Pipelined Solution for Regular Expression Matching

Automation Framework for Large-Scale Regular Expression Matching on FPGA

Real-Time Classification of Multimedia Traffic Using FPGA

Parallel Hardware Implementation of Connected Component Tree Computation

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs

FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers

High-Performance Integer Factoring with Reconfigurable Devices

Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA

Advanced Multithreading Architecture with Hardware Based Scheduling

Thermal Gradient Aware Clock Skew Scheduling for FPGAs

A Reconfigurable Computing Scheduler Optimized for Multicore Systems

An Interior Point Optimization Solver for Real Time Inter-frame Collision Detection: Exploring Resource-Accuracy-Platform Tradeoffs

GPU Versus FPGA for High Productivity Computing

Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs)

Breaking Elliptic Curve Cryptosystems Using Reconfigurable Hardware

Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures

Implementing Rainbow Tables in High-End FPGAs for Super-Fast Password Cracking

Detecting Patterns in Various Size and Angle Using FPGA

Real-Time Processing of Contrast Limited Adaptive Histogram Equalization on FPGA

Evaluation of Fault-Mitigation Schemes for Fault-Tolerant Dynamic MPSoC

Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine

Sum of Absolute Difference Implementations for Image Processing on FPGAs

Pixel Similarity Based Computation and Power Reduction Technique for H.264 Intra Prediction

Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters

Secure Protocol Implementation for Remote Bitstream Update Preventing Replay Attacks on FPGA

Online Routing Fault Detection for Reconfigurable NoC

Self-Aware Adaptation in FPGA-based Systems

Self-Test and Adaptation for Random Variations in Reliability

Memory System for a Dynamically Adaptable Pixel Stream Architecture

Test Compression for Dynamically Reconfigurable Processors

A Reconfigurable Analog Processor Based on FPAA with Coarse-Grained, Heterogeneous Configurable Analog Blocks

Customized Exposed Datapath Soft-Core Design Flow with Compiler Support

A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier

Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers

A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs

Design and Implementation of an Object-Oriented Framework for Dynamic Partial Reconfiguration

Erlang Inspired Hardware

IP Based Configurable SIMD Massively Parallel SoC

FPGA Based Engines for Genetic and Memetic Algorithms

Proof-Carrying Hardware: Runtime Formal Verification for Secure Dynamic Reconfiguration

Robust FPGA Design under Variations

On Identifying Segments of Traces for Dynamic Compilation

On Identifying Patterns in Code Repositories to Assist the Generation of Hardware Templates

Software Managed Distributed Memories in MPPAs

Design and Implementation of Real-Time Transactional Memory

Rapid Application Development on Multi-processor Reconfigurable Systems

Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs

First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells

COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization

PrEsto: An FPGA-accelerated Power Estimation Methodology for Complex Systems

Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains

Rapid Prototyping of Radiation-Tolerant Embedded Systems on FPGA

A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs

Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique

Generation of Deterministic MCU/FPGA Hybrid Systems from UML Activities

Real-Time Fault Detection and Diagnostics Using FPGA-based Architectures

A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems

NIFD: Non-intrusive FPGA Debugger -- Debugging FPGA 'Threads' for Rapid HW/SW Systems Prototyping

Exploration of Short Reads Genome Mapping in Hardware

Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options

Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA

High Density Asynchronous LUT Based on Non-volatile MRAM Technology

Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays

Design and FPGA Implementation of a 2nd Order Adaptive Delta Sigma Modulator with One Bit Quantization

Decision Forest: A Scalable Architecture for Flexible Flow Matching on FPGA

FPGA Implementations of the Round Two SHA-3 Candidates

ERCBench: An Open-Source Benchmark Suite for Embedded and Reconfigurable Computing

ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs

Pipelined FPGA Adders

Degradation Analysis and Mitigation in FPGAs

A Karatsuba-Based Montgomery Multiplier

Using Hard Macros to Reduce FPGA Compilation Time

SeqHive: A Reconfigurable Computer Cluster for Genome Re-sequencing

Reconfigurable Systems for the Zuker and Predator Algorithms for Secondary Structure Prediction of Genetic Data

LavA: An Open Platform for Rapid Prototyping of MPSoCs

OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices

Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA

A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor

A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation

Early Prediction of Hardware Complexity in HLL-to-HDL Translation

An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier

Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation

Accurate Time-to-Digital Converter Based on Xilinx's Digital Clock Managers

Dynamically Reconfigurable Vision-Chip Architecture

Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration

FPGA Based Network Traffic Analysis Using Traffic Dispersion Patterns

Reconfigurable Hardware for Power-over-Fiber Applications

Efficient FPGA Resynthesis Using Precomputed LUT Structures

Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis

Finding System-Level Information and Analyzing Its Correlation to FPGA Placement

FPGA-accelerated Attractor Computation of Scale Free Gene Regulatory Networks

A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis

An FPGA-based High-Speed, Low-Latency Processing System for High-Energy Physics

FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators

Multiplicative Square Root Algorithms for FPGAs

A Compact Transactional Memory Multiprocessor System on FPGA

Field Programmable Gate Array Implementation of Parts-Based Object Detection for Real Time Video Applications

General Purpose Computing with Reconfigurable Acceleration

MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable Technology

Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration

Dynamic Reconfiguration Optimisation with Streaming Data Decompression

Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video

Publisher's Information

2009 International Conference on Field Programmable Logic and Applications

2008 International Conference on Field Programmable Logic and Applications

2007 International Conference on Field Programmable Logic and Applications

2006 International Conference on Field Programmable Logic and Applications

International Conference on Field Programmable Logic and Applications, 2005.

Field Programmable Gate Array Implementation of Parts-Based Object Detection for Real Time Video Applications

Content Provider	IEEE Xplore Digital Library
Author	Goshorn, D. Junguk Cho Kastner, R. Mirzaei, S.
Copyright Year	2010
Abstract	The emergence of smart cameras has been fueled by increasingly advanced computing platforms that are capable of performing a variety of real-time computer vision algorithms. Smart cameras provide the ability to understand their environment. Object detection and behavior classification play an important role in making such observations. This paper presents a high-performance FPGA implementation of a generalized parts-based object detection and classifier that runs with capability of 266 frames/sec. The detection algorithm is easily reconfigured by simply loading a new representation into on-board memory, i.e., the FPGA can detect and classify a newly specified object and behavior without any changes to the hardware implementation.
Starting Page	582
Ending Page	587
File Size	1716803
Page Count	6
File Format	PDF
ISBN	9781424478422
ISSN	19461488
e-ISBN	9781424478439
DOI	10.1109/FPL.2010.114
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-31
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pixel Field programmable gate arrays Object detection Indexes Correlation Buffer storage Random access memory real-time vision smart cameras FPGA object detection hardware acceleration
Content Type	Text
Resource Type	Article

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