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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jones, D.H. Powell, A. Bouganis, C.-S. Cheung, P.Y.K. |
| Copyright Year | 2010 |
| Abstract | Heterogeneous or co-processor architectures are becoming an important component of high productivity computing systems (HPCS). In this work the performance of a GPU based HPCS is compared with the performance of a commercially available FPGA based HPC. Contrary to previous approaches that focussed on specific examples, a broader analysis is performed by considering processes at an architectural level. A set of benchmarks is employed that use different process architectures in order to exploit the benefits of each technology. These include the asynchronous pipelines common to "map" tasks, a partially synchronous tree common to "reduce" tasks and a fully synchronous, fully connected mesh. We show that the GPU is more productive than the FPGA architecture for most of the benchmarks and conclude that FPGA-based HPCS is being marginalised by GPUs. |
| Starting Page | 119 |
| Ending Page | 124 |
| File Size | 1015888 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424478422 |
| ISSN | 19461488 |
| e-ISBN | 9781424478439 |
| DOI | 10.1109/FPL.2010.32 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-08-31 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Graphics processing unit Field programmable gate arrays Benchmark testing Random access memory Computer architecture Performance evaluation Productivity FPGA High Productivity Computing GPU |
| Content Type | Text |
| Resource Type | Article |
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