NDLI: PrEsto: An FPGA-accelerated Power Estimation Methodology for Complex Systems

Content Provider	IEEE Xplore Digital Library
Author	Dam Sunwoo Wu, G.Y. Patil, N.A. Chiou, D.
Copyright Year	2010
Abstract	Reduced or bounded power consumption has become a first-order requirement for modern hardware design. As a design progresses and more detailed information becomes available, more accurate power estimations become possible but at the cost of significantly slower simulation speeds. Power simulation that is both sufficiently-accurate and fast would have a positive impact on architecture and design. In this paper, we propose PrEsto, a power modeling methodology that improves the speed and accuracy of power estimation through FPGA-acceleration. PrEsto automatically generates FPGA-based power estimators consisting of linear models that are designed to be integrated into fast, accurate FPGA-based performance simulators of microprocessors. Our prototype implementation predicts the cycle-by-cycle power dissipation of the LEON3 core and the ARM Cortex-A8 core to within 6% of a commercial gate-level power estimation tool, while running several orders of magnitude faster. The combination of simulation speed and accuracy is not only useful to architects and designers, it is fast enough to be useful for power-sensitive operating system and application developers.
Starting Page	310
Ending Page	317
File Size	1439295
Page Count	8
File Format	PDF
ISBN	9781424478422
ISSN	19461488
e-ISBN	9781424478439
DOI	10.1109/FPL.2010.69
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-31
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Accuracy Benchmark testing Computational modeling Training Mathematical model Frequency modulation Simulation FPGA-acceleration Power estimation
Content Type	Text
Resource Type	Article

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