NDLI: Architecture efficiency of application-specific processors: A 170Mbit/s $0.644mm^{2}$ multi-standard turbo decoder

Content Provider	IEEE Xplore Digital Library
Author	Al-Khayat, R. Baghdadi, A. Jezequel, M.
Copyright Year	2012
Description	Author affiliation: Institut Mines-Telecom, Electronics Department, Telecom Bretagne, Technopôle Brest Iroise CS 83818, 29238, Université Européenne de Bretagne, France (Al-Khayat, R.; Baghdadi, A.; Jezequel, M.)
Abstract	Architecture efficiency, in terms of performance/area, of application-specific processors is directly related to the devised instruction set and pipeline stages usage. Most of recently proposed works on application-specific instruction-set processors (ASIP) do not consider or present this key point explicitly. In this paper, we consider the challenging turbo decoding application where many recent implementations have been proposed to accommodate the related large flexibility and high throughput requirements. The paper demonstrates how the architecture efficiency of instruction-set based processors can be considerably improved by minimizing the pipeline idle time. A complete ASIP-based turbo decoder is proposed with further contributions on interleaving generators, extrinsic information exchange, and rapid reconfiguration. While supporting 3GPP LTE,WiMAX and DVB-RCS turbo codes, the proposed implementation achieves a throughput of 170Mbps with $0.644mm^{2}$ @65nm CMOS technology. The proposed ASIP-based turbo decoder exhibits a high architecture efficiency of 3.12 $bit/cycle/iteration/mm^{2}.$
Starting Page	1
Ending Page	7
File Size	2287492
Page Count	7
File Format	PDF
ISBN	9781467328951
e-ISBN	9781467328968
e-ISBN	9781467328944
DOI	10.1109/ISSoC.2012.6376368
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-10
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Standards Throughput WiMAX Digital video broadcasting Slag ARP interleaver SoC design Architecture efficiency ASIP Pipeline Turbo codes LTE DVB-RCS QPP interleaver
Content Type	Text
Resource Type	Article

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