NDLI: Asynchronous parallel MPSoC simulation on the Single-Chip Cloud Computer

Content Provider	IEEE Xplore Digital Library
Author	Roth, C. Reder, S. Erdogan, G. Sander, O. Almeida, G.M. Bucher, H. Becker, J.
Copyright Year	2012
Description	Author affiliation: Karlsruhe Institute of Technology (KIT), Institute for Information Processing Technology (ITIV), Germany (Roth, C.; Reder, S.; Erdogan, G.; Sander, O.; Almeida, G.M.; Bucher, H.; Becker, J.)
Abstract	The growing complexity of embedded applications currently causes a trend towards multi-core processors in the embedded domain. Time-consuming detailed simulations make the design of such systems increasingly sophisticated. In this work, applicability of Parallel Discrete Event Simulation (PDES) in the context of cycle-accurate Multi-Processor System-on-Chip (MPSoC) simulation is investigated on the Single-chip Cloud Computer (SCC) from Intel. The presented strategy targets asynchronous parallel model execution where only adjacent model partitions need to synchronize with each other in order to advance in simulation time. Performance of the approach is evaluated by means of a scalable cycle-accurate MPSoC model called HeMPS. For a 8×8 RTL model measurements reveal a speedup versus sequential RTL simulation of 25.3×. When exchanging RTL processing elements by cycle-accurate simulators a speedup of 56.3× versus sequential RTL simulation is obtained. These results promise good suitability of the asynchronous strategy for detailed parallel MPSoC simulation on an architecture like the SCC.
Starting Page	1
Ending Page	8
File Size	818644
Page Count	8
File Format	PDF
ISBN	9781467328951
e-ISBN	9781467328968
e-ISBN	9781467328944
DOI	10.1109/ISSoC.2012.6376364
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-10
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Tiles Synchronization Kernel Computational modeling Receivers Computer architecture Computers
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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