NDLI: An Effective IP Reuse Methodology for Quality System-on-Chip Design

Content Provider	IEEE Xplore Digital Library
Author	Sarkar, S. Shinde, S. Chandar, S.G.
Copyright Year	2005
Description	Author affiliation: Texas Instrum., Bangalore (Sarkar, S.; Shinde, S.; Chandar, S.G.)
Abstract	Intellectual property (IP) reuse improves system-on-a-chip (SoC) design productivity, and helps to meet design quality and time-to-market goals. However, IP quality issues in terms of inadequate test coverage, low power capability, absence of functional features etc. has led to reduced benefits from reuse. This is because the IP is usually designed for use in one chip and later on (re)used in chips having different requirements. Hence, part of SoC design productivity is spent in enhancing the IP to the desired quality level. As updated versions of the IP may be released several times during the SoC design phase, managing the design database poses challenge with respect to the IP enhancements. In this paper, we describe the methodology that we successfully followed in our SoC design. It consists of enhancing the IPs for meeting the desired goals, validating the changes and controlling its version in the design database. It is required to integrate three mission critical IPs developed by the customer. Certain modifications to the customer IPs were called for to meet SoC design goals and obtain a better quality of implementation.
Starting Page	104
Ending Page	107
File Size	798601
Page Count	4
File Format	PDF
ISBN	0780392949
DOI	10.1109/ISSOC.2005.1595655
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-11-17
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip Productivity Databases Time to market Testing Signal design Digital signal processing Instruments Intellectual property Mission critical systems
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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