NDLI: A 16-bit 1MS/s 44mW successive approximation register analog-to-digital converter achieving signal-to-noise-and-distortion-ratio of 94.3dB

Content Provider	IEEE Xplore Digital Library
Author	Yingying Chi Dongmei Li Zhihua Wang
Copyright Year	2013
Description	Author affiliation: Dept. of Electron. Eng., Tsinghua Univ., Beijing, China (Dongmei Li) \|\| Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China (Yingying Chi; Zhihua Wang)
Abstract	A relatively low-power 16-bit 1MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the typical structure of SAR ADC, some effective techniques including bootstrapped sampling-switch used to suppress nonlinear distortion, dynamic comparator to reduce power dissipation and the offset-calibration to ensure conversion accuracy have been employed. The off-chip search algorithm is developed against the harmonic distortion resulted from capacitor mismatch. Simulation with parasitism extracted from the layout demonstrates that the ADC achieves signal-to-noise-and-distortion-ratio (SNDR) of 94.3dB at 1MSamples/s, 500KHz input frequency and consumes 44mW from a 1.8V power supply. With the 0.18μm complementary metal-oxide semiconductor (CMOS) process and metal-insulator-metal (MIM) capacitor, the ADC core including decoupling capacitors occupies an active area of 1.0mm×1.4mm.
Sponsorship	IEEE Electron Devices Soc.
Starting Page	1
Ending Page	2
File Size	905564
Page Count	2
File Format	PDF
ISBN	9781467325233
DOI	10.1109/EDSSC.2013.6628134
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-03
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitors Calibration Approximation methods Noise Layout CMOS integrated circuits Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 0.45mW 12b 12.5MS/s SAR ADC with digital calibration

A successive approximation A/D converter with 16 bit 200 kS/s in 0.6 /spl mu/m CMOS using self calibration and low power techniques

An 8-bit 2 MS/s successive approximation register analog-to-digital converter for bioinformatics and computational biology Application

1MS/s low power successive approximations register ADC for 67-fJ/conversion-step

A $0.004mm^{2}$ single-channel 6-bit 1.25GS/s SAR ADC in 40nm CMOS

Design of binary architecture for Successive Approximation Analog-to-Digital Converter

A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS

Charge scaling 10-bit successive approximation A/D converter with reduced input capacitance

A novel 10bit 90MS/s 2b/cycle SAR ADC

A 16-bit 1MS/s 44mW successive approximation register analog-to-digital converter achieving signal-to-noise-and-distortion-ratio of 94.3dB

Similar Documents

A 0.45mW 12b 12.5MS/s SAR ADC with digital calibration

A successive approximation A/D converter with 16 bit 200 kS/s in 0.6 /spl mu/m CMOS using self calibration and low power techniques

An 8-bit 2 MS/s successive approximation register analog-to-digital converter for bioinformatics and computational biology Application

1MS/s low power successive approximations register ADC for 67-fJ/conversion-step

A $0.004mm^{2}$ single-channel 6-bit 1.25GS/s SAR ADC in 40nm CMOS

Design of binary architecture for Successive Approximation Analog-to-Digital Converter

A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS

Charge scaling 10-bit successive approximation A/D converter with reduced input capacitance

A novel 10bit 90MS/s 2b/cycle SAR ADC

A 16-bit 1MS/s 44mW successive approximation register analog-to-digital converter achieving signal-to-noise-and-distortion-ratio of 94.3dB