NDLI: Dual cycle shift data-weighted averaging technique for multi-bit Sigma-Delta Modulators

Content Provider	IEEE Xplore Digital Library
Author	Xiaofen Ma Jian Xu Xiaobo Wu
Copyright Year	2009
Description	Author affiliation: Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China (Xiaofen Ma; Jian Xu; Xiaobo Wu)
Abstract	Data weighted averaging (DWA) is the most popular Dynamic Element Matching (DEM) technique to reduce the effects of DAC nonlinearity in multi-bit Sigma-Delta Modulators (MBSDM). However, due to the non-symmetry of the unit-elements in multi-bit DAC, in-band signal-dependent tones always appear when a low oversampling ratio (OSR) is employed in traditional DWA. Therefore, a novel DEM technique, dual cycle shift DWA (DCSDWA), is proposed to deal with the tone problem in this paper. Compared with other modified DWA techniques, DCSDWA is a more effective one with simple implementation. Using the proposed technique in a 4th-order MBSDM with an OSR of 32, the maximum in-band tone is reduced to 6 dB when a random DAC-element mismatching error of 0.5% is assumed. In addition, it results in a better linearity of signal-to-noise distortion ratio (SNDR) versus different input signal and a wider dynamic range (DR). The simulation results prove that the proposed DCSDWA is suitable for low OSR applications (OSR⩾8) with a good performance.
Starting Page	174
Ending Page	177
File Size	5642166
Page Count	4
File Format	PDF
ISBN	9781424442973
DOI	10.1109/EDSSC.2009.5394163
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-25
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delta-sigma modulation Mathematical model Counting circuits Feedback Calibration Signal processing Clocks Linearity Distortion Dynamic range Dual Cycle Shift DWA Multi-bit Sigma-Delta modulators DAC nonlinearity
Content Type	Text
Resource Type	Article

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