NDLI: An efficient clock tree synthesis method in physical design

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An efficient clock tree synthesis method in physical design

Content Provider	IEEE Xplore Digital Library
Author	Guirong Wu Song Jia Yuan Wang Ganggang Zhang
Copyright Year	2009
Description	Author affiliation: Key Laboratory of Microelectronics Devices and Circuits, Institute of Microelectronics, Peking University, Beijing, China (Guirong Wu; Song Jia; Yuan Wang; Ganggang Zhang)
Abstract	This paper proposes a method aiding in low clock skew applicable to the mainstream industry clock tree synthesis (CTS) design flow. The original clock root is partitioned into several pseudo clock sources at the gate level. The automatic place and route (APR) tool may synthesize the clock tree with better performance in clock skew because each pseudo clock source drives smaller number of fan out. The proposed method is applied to a chip level clock tree network and achieves good results.
Starting Page	190
Ending Page	193
File Size	6469230
Page Count	4
File Format	PDF
ISBN	9781424442973
DOI	10.1109/EDSSC.2009.5394159
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-25
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Design methodology Frequency synchronization Image edge detection Navigation Histograms Signal processing algorithms Frequency estimation Maximum likelihood detection Maximum likelihood estimation Low Clock Skew Physical Design Clock Tree Synthesis
Content Type	Text
Resource Type	Article

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