NDLI: Performance, power and scalability analysis of HEVC interpolation filter using FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Gomez-Pulido, J.A. Cordeiro, P.J. Assuncao, P.A.
Copyright Year	2015
Description	Author affiliation: Dept. of Tech. Comput. & Comm., Univ. of Extremadura, Caceres, Spain (Gomez-Pulido, J.A.) \|\| Inst. de Telecomun., Inst. Politec. de Leiria, Leiria, Portugal (Cordeiro, P.J.; Assuncao, P.A.)
Abstract	Motion compensation is the most time-consuming stage of the most recent video coding standard, and uses an interpolation filter to handle efficiently the video bitstream. When high resolutions, low power budgets and huge amount of video data are demanded, exploiting parallelism is a mandatory task. In this paper we propose an implementation of the interpolation filter using the reconfigurable hardware technology, in order to build parallel computing systems that offer a high performance, in terms of computing time and power consumption. The timing simulations and energy analysis performed on different devices show that the on-chip replication of the filter provides high speedups with regard to general purpose processors. The good experimental results motivates us to do a first approach to scalable parallel computing systems where parallelism is exploited from fine to coarse grain, multiplying the speedups obtained. In particular, we propose an on-chip multiprocessor system where filters act as coprocessors of embedded high-performance and low-power microprocessors, linked among them by point-to-point buses. This on-chip architecture can be applied to high performance computing systems based on the same reconfigurable hardware technology.
Starting Page	1
Ending Page	6
File Size	508291
Page Count	6
File Format	PDF
e-ISBN	9781479985692
DOI	10.1109/EUROCON.2015.7313689
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-08
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Program processors Interpolation Parallel processing Power demand Decoding Hardware power consumption Video coding motion compensation interpolation HEVC reconfigurable hardware FPGA performance scalability
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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