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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ren Chen Neungsoo Park Prasanna, V.K. |
| Copyright Year | 2013 |
| Description | Author affiliation: Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA (Ren Chen; Prasanna, V.K.) || Dept. of Comput., Sci. & Eng., Konkuk Univ., Seoul, South Korea (Neungsoo Park) |
| Abstract | Throughput is a key performance metric for streaming FFT architectures. However, increasing spatial parallelism to improve throughput introduces complex routing, thus resulting in high power consumption. In this paper, we propose a high throughput energy efficient parallel FFT architecture based on Cooley-Tukey algorithm. Multiple pipeline FFT processors using time-multiplexing are utilized to perform FFT computation tasks in parallel. This design realizes high performance using task-level parallelism and avoids complex routing. Furthermore, to reduce the memory power consumption, a periodic memory activation (PMA) scheme is developed. By analyzing energy efficiency (defined as GOPS/Joule) asymptotically, we show that our design achieves a low energy efficiency complexity while satisfying a high-throughput requirement. For N-point FFT (64 ≤ N ≤ 4096), our proposed architecture achieves 50 ~ 63 GOPS/Joule, i.e., up to 78% of the Peak Energy Efficiency of FFT designs on FPGAs. Compared with a state-of-the-art design, our design improves the energy efficiency (defined as GOPS/Joule) by 17% to 26% with the same throughput. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 319807 |
| Page Count | 6 |
| File Format | |
| e-ISBN | 9781479913657 |
| DOI | 10.1109/HPEC.2013.6670343 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-09-10 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Program processors Power demand Pipelines Computer architecture Parallel processing Throughput Field programmable gate arrays |
| Content Type | Text |
| Resource Type | Article |
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