NDLI: Thermo-mechanical stress characterization of tungsten-fill through-silicon-via

Content Provider	IEEE Xplore Digital Library
Author	Dao, T. Triyoso, D.H. Mora, R. Kropewnicki, T. Griesbach, B. Booker, D. Petras, M. Adams, V.
Copyright Year	2010
Description	Author affiliation: Freescale Semiconductor, Tempe, Arizona, USA (Petras, M.; Adams, V.) \|\| Freescale Semiconductor, Austin, Texas, USA (Dao, T.; Triyoso, D.H.; Mora, R.; Kropewnicki, T.; Griesbach, B.; Booker, D.)
Abstract	Thermo-mechanical stress of tungsten-filled (W-fill) through-silicon-via (TSV) is strongly depending on via shape, size and inter-via spacing, which places constraints on TSV design, including 2-D integrated circuit layout and 3-D structure profile. This paper summarizes these constraints and co-relations among thick (up to 1.2μm) tungsten (W) film, W-fill TSV, and surrounding silicon structures, using Flexus bowing measurement, Wright etch method, and also 3-D TSV stress simulations. In this study, the stress was found to be primarily tensile, and tended to be much higher along the longitudinal ends of the TSV compared to the longitudinal side wall. For an isolated TSV of given width and depth: with 30μm length the stress is 45% greater compared to the case of 7μm length. For an array of TSV with given length, width, and depth: larger spacing along the longitudinal axis (length directions) resulted in 35% lower stress at the longitudinal ends of the TSV, while smaller spacing along the transverse axis (width directions) of the TSV resulted in a 46% lower tensile stress. However, along the longitudinal side walls, the tensile stress increases by 200 MPa as the spacing along the transverse axis decreases between neighboring TSV.
Starting Page	96
Ending Page	99
File Size	574943
Page Count	4
File Format	PDF
ISBN	9781424450633
ISSN	1930885X
DOI	10.1109/VTSA.2010.5488931
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-26
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Thermomechanical processes Thermal stresses Through-silicon vias Tensile stress Shape Integrated circuit layout Tungsten Semiconductor films Silicon Stress measurement
Content Type	Text
Resource Type	Article

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