NDLI: Key sub 1nm EOT CMOS enabler by comprehensive PMOS design

Content Provider	IEEE Xplore Digital Library
Author	Tseng, J. Ragnarsson, L.-A. Schram, T. Akheyar, A. Okuno, Y. Li, Z.L. Aoulaiche, M. Rohr, E. Witters, T. Adelmann, C. Delabie, A. Paraschiv, V. Kerner, C. Xiong, K. Mueller, M. Hoffmann, T. Absil, P. Biesemans, S.
Copyright Year	2010
Description	Author affiliation: IMEC, assignee at IMEC from, Kapeldreef 75, B-3001 Leuven, Belgium (Ragnarsson, L.-A.; Schram, T.; Li, Z.L.; Aoulaiche, M.; Rohr, E.; Witters, T.; Adelmann, C.; Delabie, A.; Paraschiv, V.; Kerner, C.; Hoffmann, T.; Absil, P.; Biesemans, S.) \|\| NXP-TSMC Research Center, Kapeldreef 75, B-3001 Leuven, Belgium (Xiong, K.; Mueller, M.) \|\| TSMC, Kapeldreef 75, B-3001 Leuven, Belgium (Tseng, J.) \|\| Panasonic, Kapeldreef 75, B-3001 Leuven, Belgium (Okuno, Y.) \|\| Infineon, Kapeldreef 75, B-3001 Leuven, Belgium (Akheyar, A.)
Abstract	A high performance CMOS HK/MG sub 1nm EOT solution is demonstrated. The drive currents at Ioff=100 nA/μm with VDD=1 V are 1.25 mA/μm and 0.56 mA/μm for n and pMOS respectively without strain boost. Through a novel process integration design, PMOS EWF roll-off and NBTI problems with EOT scaling are overcome until sub 1nm EOT region. The PMOS −0.25V Vt @1um Lg and NBTI 10 years life time @0.7V overdrive are thus offered with 0.94nm EOT. Mechanisms and guidelines for solving theses issues are provided after a comprehensive study here. These concepts are beneficial to either gate-first or gate-last approach with EOT scaling.
Starting Page	116
Ending Page	117
File Size	614632
Page Count	2
File Format	PDF
ISBN	9781424450633
ISSN	1930885X
DOI	10.1109/VTSA.2010.5488923
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-26
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Annealing Niobium compounds Titanium compounds Guidelines Hafnium oxide Capacitive sensors CMOS technology Process design High-K gate dielectrics Degradation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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