NDLI: Improved Layout Dependence in High Performance SiGe Channel CMOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Liu, P.W. Chiang, W.T. Huang, Y.T. Tsai, T.L. Tsai, C.H. Tsai, C.T. Ma, G.H.
Copyright Year	2008
Description	Author affiliation: United Microelectron. Corp. (UMC), Tainan (Liu, P.W.; Chiang, W.T.; Huang, Y.T.; Tsai, T.L.; Tsai, C.H.; Tsai, C.T.; Ma, G.H.)
Abstract	The device degradation problem due to compressive STI in devices with narrow width or small diffusion length can be greatly relieved in SiGe channel devices with the post-STI epitaxy process. The (110)SiGe PMOS realizes 77% current gain over (100)Si PMOS at 1um gate width, and current gain is increased to 112% at 0.12um gate width. A 42% current improvement in (100)SiGe NMOS at 0.12um gate width is also reported. Moreover, for diffusion length ranging from 2.71um to 0.26um, less than 4% current variation is obtained in SiGe channel devices compared to the 8~12% current variation in Si channel devices. The improved layout dependence is resulted from the lower STI stress in post-STI SiGe epitaxy process.
Starting Page	161
Ending Page	162
File Size	662951
Page Count	2
File Format	PDF
ISBN	9781424416141
ISSN	1524766X
DOI	10.1109/VTSA.2008.4530847
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-21
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon germanium Germanium silicon alloys CMOSFETs MOS devices Degradation Compressive stress Epitaxial growth Microelectronics Nanoscale devices Piezoresistance
Content Type	Text
Resource Type	Article

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