NDLI: PSDG MOSFET

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2015 International Symposium on VLSI Technology, Systems and Applications

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2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

2006 International Symposium on VLSI Technology, Systems, and Applications

Table of contents

Semiconductor Manufacturing Technology in the 21st Century

Challenges for process and product integration at 45nm

3D System Integration Technologies

Future Memory Devices - from Stacked memory, Gain memory, Single-electron memory to Molecular memory

Analysis of Electron and Hole Distributions on Scaled NBit Flash Cells

P-channel SONOS Transient Current Modeling for Program and Erase

Understanding of the Leakage Components and Its Correlation to the Oxide Scaling on the SONOS Cell Endurance and Retention

High-κ Hf-based charge trapping layer with $Al_{2}O_{3}$ blocking oxide for high-density flash memory

VDD Scaling for FinFET Logic and Memory Circuits: the Impact of Process Variations and SRAM Stability

Novel T shape structure PCM and Electrical-Thermal Characteristics

A New Read Method by Using DIBL Characteristics in Nitride Storage Device

Writing Architecture for Magnetic Random Access Memory with Negative Pulse Writing Scheme

Strained Si and the Future Direction of CMOS

Optimization of Source/Drain Extension for Robust Speed Performance to Process Variation in Undoped Double-Gate CMOS

Mo Gate Deformation Induced by Laser Annealing Process

Low-Leakage Diode String Design without Extra Circuits for ESD Applications

Investigation on RF Characteristics of Stacked P-I-N Polysilicon Diodes for ESD Protection Design in 0.18-μm CMOS Technology

65nm SOI CMOS Technology for High Performance Microprocessor Application

A Promising Planar Transistor with in-situ Doped Selective Si Epitaxy Technology (GORES MOSFET) for 32nm node and beyond

Strain-Induced Channel Backscattering Modulation in Nanoscale CMOSFETs

Vapor and Solution Deposited Organic Thin Film Transistors

Printed transistors and passive components for low-cost electronics applications

Future Prospects of Flexible, Large-Area Sensors and Actuators with Organic Transistor ICs

Tubes, Ribbons and Wires for Flexible Electronics

Printed Electronics for System Application

Advanced Substrate Engineering for the Nanotechnology Era

A CMOS Bulk-Micromachined Thermal Imager

Impact of Back Gate Bias on Hot-Carrier Effects of n-channel Tri-Gate FETs (TGFETs)

Ultra-Thin SOI CMOS Using Laser Spike Anneal

Effect of Oxygen Absorption on Contact Resistance between Metal and Carbon Nano Tubes (CNTs)

A Novel Deep Trench Isolation Featuring Airgaps for a High-Speed 0.13μm SiGe:C BiCMOS Technology

Beyond Scaling - Realizing Value Through the Integration of Memory and Autonomic Chip Features

Trench DRAM Technologies for the 50nm Node and Beyond

Overview and Future Challenge of Floating Body Cell (FBC) Technology for Embedded Applications

Stack DRAM Technologies for the Future

A Novel Dram Cell Design and Process for 70NM Generation

Reliability Assessment of the Embedded DRAM Technology with PMOSFET Transfer Transistor and High-K Dielectrics (Ta2O5) MIM Capacitor

Metal Gate Technology for 45nm and Beyond

Electron Trapping Processes in High-K Gate Dielectrics and Nature of Traps

HfSiON Gate Dielectric for 45nm Node Low-Power Device

Detection of Trap Generation in High-κ Gate Stacks due to Constant Voltage Stress

Relationship of HfO2 Material Properties and Transistor Performance

HfxTayNz Metal Gate Electrodes for Advanced MOS Devices Applications

Impact of WSix Metal Gate Stoichiometry on Fully Depleted SOI MOSFETs Electrical Properties

NMOS and PMOS Metal Gate Transistors with Junctions Activated by Laser Annealing

Tunable Workfunction for Fully Silicied Gates (FUSI) and Proposed Mechanisms

Roadblocks and Critical Aspects of Cleaning for Sub-65nm Technologies

Effect of H2 Addition during Cu Thin Film Sputtering

Resistance Increase in Metal Nano-wires

Die-Based Electromigration Characterization For Copper/Low-K Dual Damascene Interconnects

Integration of Cu Damascene with Pore-sealed PECVD Porogen Low-k (k=2.5) Dielectrics for 65nm Generation

Wafer-Level Compliant Bump for 3D Chip-Stacking

Strained-SOI Technology for High-Speed CMOS Operation

RF Extrinsic Resistance Extraction Considering Neutral-Body Effect for Partially-Depleted SOI MOSFETs

Hot Electrons Associated with the Long-Range Coulomb Interaction under the High-Density Regime

A New Series Resistance and Mobility Extraction Method by BSIM Model for Nano-Scale MOSFETs

Coupling Advanced Atomistic Process and Device Modeling for Optimizing Future CMOS Devices

An Asymmetrical Double-Gate VCO with Wide Frequency Range

IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech).

2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672)

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)

Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications

1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers

1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers

1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers

International Symposium on VLSI Technology, Systems and Applications,

PSDG MOSFET

Content Provider	IEEE Xplore Digital Library
Author	Deyuan Xiao Chen, G. Lee, R. Lu, D. Tan, L. Liu, Y. Shen, C.C. Jong Woo Kim
Copyright Year	2006
Description	Author affiliation: Memory Technol. Dev. Center, Semicond. Manuf. Int. Corp., Shanghai (Deyuan Xiao; Chen, G.; Lee, R.; Lu, D.; Tan, L.; Liu, Y.; Shen, C.C.; Jong Woo Kim)
Abstract	A new planar split dual gate MOSFET device (PSDG MOSFET) is reported for the first time. The theoretical calculation, 3D device simulation as well as the experiment data show that with the two independent split dual gates in PSDG MOSFET, it can provide dynamical control of the device characteristics, such as threshold voltage (Vt) and sub-threshold swing (SS) as well as the Idsat of the device
Starting Page	1
Ending Page	2
File Size	1799087
Page Count	2
File Format	PDF
ISBN	1424401814
ISSN	1524766X
DOI	10.1109/VTSA.2006.251068
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-04-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET circuits Threshold voltage Modeling Voltage control Leakage current Semiconductor device manufacture Partial response channels Energy management CMOS technology Dielectrics
Content Type	Text
Resource Type	Article

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