NDLI: The revolutionary and truly 3-dimensional 25F/sup 2/ SRAM technology with the smallest S/sup 3/ ( stacked single-crystal Si) cell, 0.16um/sup 2/, and SSTFT (atacked single-crystal thin film transistor) for ultra high density SRAM

Content Provider	IEEE Xplore Digital Library
Author	Soon-Moon Jung Jaehoon Jang Wonseok Cho Jaehwan Moon Kunho Kwak Bonghyun Choi Byungjun Hwang Hoon Lim Jaehun Jeong Jonghyuk Kim Kinam Kim
Copyright Year	2003
Description	Author affiliation: R&D Center, Samsung Electron., Kyunggi-Do, South Korea (Soon-Moon Jung; Jaehoon Jang; Wonseok Cho; Jaehwan Moon; Kunho Kwak; Bonghyun Choi; Byungjun Hwang; Hoon Lim; Jaehun Jeong; Jonghyuk Kim; Kinam Kim)
Abstract	The smallest 25F/sup 2/ SRAM cell size of 0.16um/sup 2/ is realized by S/sup 3/ cell technology and SSTFT with 193nm ArF lithography process. The stacked single-crystal thin film is developed and used for the first time in the SRAM cell to make the SRAM products comparative to the DRAM products in the density and the cost. The load PMOS and pass NMOS transistors are stacked over the planar pull-down NMOS transistors to drastically reduce the cell size. In this study, the dream of truly 3D memory device is achieved by fabricating 64M bit density SRAM.
Starting Page	228
Ending Page	229
File Size	286627
Page Count	2
File Format	PDF
ISBN	0780382897
DOI	10.1109/VLSIT.2004.1345495
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Thin film transistors MOSFETs Threshold voltage MOS devices Stacking Moon Research and development Lithography Semiconductor films
Content Type	Text
Resource Type	Article

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