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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zamdmer, N. Jonghae Kim Trzcinski, R. Plouchart, J.-O. Narasimha, S. Khare, M. Wagner, L. Chaloux, S. |
| Copyright Year | 2003 |
| Description | Author affiliation: Dev. Center, IBM Semicond. Res., Hopewell Junction, NY, USA (Zamdmer, N.; Jonghae Kim; Trzcinski, R.; Plouchart, J.-O.; Narasimha, S.; Khare, M.; Wagner, L.; Chaloux, S.) |
| Abstract | SOI CMOS technology offers low parasitic junction capacitance, and therefore provides speed and power enhancements to digital applications compared to bulk CMOS. It is also emerging as a good candidate for high-performance SoC, with integratable RF circuits that operate beyond 30-GHz already demonstrated at the 130-nm technology node. The digital aspects of the base 90-nm SOI technology were previously reported. This paper presents the RF performance of this technology, and shows that the capabilities of CMOS technology are expanding into the millimeter-wave regime. |
| Starting Page | 98 |
| Ending Page | 99 |
| File Size | 164769 |
| Page Count | 2 |
| File Format | |
| ISBN | 0780382897 |
| DOI | 10.1109/VLSIT.2004.1345415 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-06-15 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | CMOS technology CMOS digital integrated circuits Millimeter wave circuits Millimeter wave technology Radio frequency Millimeter wave measurements Integrated circuit technology Parasitic capacitance Varactors Performance evaluation |
| Content Type | Text |
| Resource Type | Article |
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