NDLI: A 45 nm gate length high performance SOI transistor for 100 nm CMOS technology applications

Content Provider	IEEE Xplore Digital Library
Author	Celik, M. Krishnan, S. Fuselier, M. Wei, A. Wu, D. En, B. Cave, N. Abramowitz, P. Byoung Min Pelella, M. Ping Yeh Burbach, G. Taylor, B. Yongjoo Jeon Wen-Jie Qi Ruigang Li Conner, J. Yeap, G. Woo, M. Mendicino, M. Karlsson, O. Wristers, D.
Copyright Year	2002
Description	Author affiliation: Digital DNA Labs., Austin, TX, USA (Celik, M.)
Abstract	In this report, a high performance silicon-on-insulator (SOI) transistor for the 100 nm CMOS technology node is presented. Partially depleted (PD) transistors were fabricated in a 1000 /spl Aring/-thick silicon film with gate lengths down to 45 nm, using a 16 /spl Aring/ nitrided gate oxide. At an operating voltage of 1.2 V, self-heated drive currents of 940 /spl mu/A//spl mu/m and 460 /spl mu/A//spl mu/m were achieved at 20 nA//spl mu/m for NMOS and PMOS respectively. Floating body effects (FBE) were minimized by special diode junction engineering to achieve maximum overall performance. A measured median stage delay of 6 ps was achieved on an inverter-fan-out-1 ring oscillator at 1.3 V at a total N+P leakage of 30 nA//spl mu/m. The exceptional AC performance of this technology is among the highest reported in the literature at this low transistor leakage and operating voltage.
Starting Page	166
Ending Page	167
File Size	289175
Page Count	2
File Format	PDF
ISBN	078037312X
DOI	10.1109/VLSIT.2002.1015435
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Silicon on insulator technology Delay Voltage Ring oscillators Capacitance Inverters Hysteresis Semiconductor films MOS devices
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

High-performance 80-nm gate length SOI-CMOS technology with copper and very-low-k interconnects

Sub-100 nm CMOS/SIMOX delay modeling by time-dependent gate capacitance model

Simulation-based assessment of 50 nm double-gate SOI CMOS performance

Scalability revisited: 100 nm PD-SOI transistors and implications for 50 nm devices

100 nm gate length high performance/low power CMOS transistor structure

A high speed and low power on CMOS/SOI technology

A high performance 0.13 /spl mu/m SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL

60 nm gate length dual-Vt CMOS for high performance applications

Ultrafast low-power operation of p/sup +/-n/sup +/ double-gate SOI MOSFETs

A 45 nm gate length high performance SOI transistor for 100 nm CMOS technology applications

Similar Documents

High-performance 80-nm gate length SOI-CMOS technology with copper and very-low-k interconnects

Sub-100 nm CMOS/SIMOX delay modeling by time-dependent gate capacitance model

Simulation-based assessment of 50 nm double-gate SOI CMOS performance

Scalability revisited: 100 nm PD-SOI transistors and implications for 50 nm devices

100 nm gate length high performance/low power CMOS transistor structure

A high speed and low power on CMOS/SOI technology

A high performance 0.13 /spl mu/m SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL

60 nm gate length dual-Vt CMOS for high performance applications

Ultrafast low-power operation of p/sup +/-n/sup +/ double-gate SOI MOSFETs

A 45 nm gate length high performance SOI transistor for 100 nm CMOS technology applications