NDLI: Novel DRAM cell transistor with asymmetric source and drain junction profiles improving data retention characteristics

Content Provider	IEEE Xplore Digital Library
Author	Ahn, S.J. Jung, G.T. Cho, C.H. Shin, S.H. Lee, J.Y. Lee, J.G. Jeong, H.S. Kinam Kim
Copyright Year	2002
Description	Author affiliation: Semicond. R&D Center, Samsung Electron. Co. Ltd., Kyunggi-Do, South Korea (Ahn, S.J.; Jung, G.T.; Cho, C.H.; Shin, S.H.; Lee, J.Y.; Lee, J.G.; Jeong, H.S.; Kinam Kim)
Abstract	A novel DRAM cell transistor with an asymmetric source and drain structure is proposed, for the first time, to realize reliable high density DRAM below 0.12 /spl mu/m. The new cell structure could provide the optimized source and drain junction profiles independently. The junction profile at the storage node (SN) was designed to reduce electric field to minimize junction leakage current and thereby improving data retention time. On the other hand, the junction profile at the bit-line direct contact node (DC) was designed to suppress short channel effects of a cell transistor. It is considered to be highly scalable for device scaling and to solve fine printing and precise alignment requirements. The validity of the approach was directly confirmed by improvement in the refresh times of 512 Mb DRAM which was fabricated with 0.12 /spl mu/m DRAM technology.
Starting Page	176
Ending Page	177
File Size	273147
Page Count	2
File Format	PDF
ISBN	078037312X
DOI	10.1109/VLSIT.2002.1015441
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Leakage current Tin Boron Subthreshold current Doping profiles Research and development Printing Degradation Threshold voltage
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Ultra-low leakage junction engineering of cell transistor by raised source/drain for logic-compatible 28-nm embedded DRAM

One-transistor bistable-body tunnel SRAM

A Novel Body Effect Reduction Technique to Recessed Channel Transistor Featuring Partially Insulating Layer Under Source and Drain : Application to Sub-50nm DRAM Cell

Drain leakage fluctuation reduction in the recessed channel array transistor DRAM with the elevated source-drain

Reliability Studies on Non Planar DRAM Cell Transistor

Improvement of Data Retention Time Property by Reducing Vacancy-Type Defect in DRAM Cell Transistor

Enhancement of data retention time in DRAM using step gated asymmetric (STAR) cell transistors

Packaging process induced retention degradation of 256 Mbit DRAM with negative wordline bias

Study on the Retention Time of Body Tied FINFET DRAM with <100> Channel Directional Wafer

Novel DRAM cell transistor with asymmetric source and drain junction profiles improving data retention characteristics

Similar Documents

Ultra-low leakage junction engineering of cell transistor by raised source/drain for logic-compatible 28-nm embedded DRAM

One-transistor bistable-body tunnel SRAM

A Novel Body Effect Reduction Technique to Recessed Channel Transistor Featuring Partially Insulating Layer Under Source and Drain : Application to Sub-50nm DRAM Cell

Drain leakage fluctuation reduction in the recessed channel array transistor DRAM with the elevated source-drain

Reliability Studies on Non Planar DRAM Cell Transistor

Improvement of Data Retention Time Property by Reducing Vacancy-Type Defect in DRAM Cell Transistor

Enhancement of data retention time in DRAM using step gated asymmetric (STAR) cell transistors

Packaging process induced retention degradation of 256 Mbit DRAM with negative wordline bias

Study on the Retention Time of Body Tied FINFET DRAM with <100> Channel Directional Wafer

Novel DRAM cell transistor with asymmetric source and drain junction profiles improving data retention characteristics