NDLI: High performance CMOS operation of strained-SOI MOSFETs using thin film SiGe-on-insulator substrate

Content Provider	IEEE Xplore Digital Library
Author	Mizuno, T. Sugiyama, N. Tezuka, T. Numata, T. Takagi, S.
Copyright Year	2002
Description	Author affiliation: MIRAI Project, Assoc. of Super-Adv. Electron. Technol., Kawasaki, Japan (Mizuno, T.; Sugiyama, N.; Tezuka, T.; Numata, T.; Takagi, S.)
Abstract	We demonstrate high performance CMOS operation of fully depleted (FD) and partially depleted (PD) strained-SOI MOSFETs on a new thin-film-SGOI substrate with high Ge content (25%) fabricated by the combination of SIMOX and ITOX technologies, without using the usual thick SiGe buffer layers. We verify high electron (85%) and hole (50%) mobility enhancement of strained-SOI MOSFETs against the universal carrier mobility. It is demonstrated, as a result, that the gate delay time of strained-SOI CMOS is improved by about 70%, compared to that of control-SOI CMOS. Moreover, we also discuss both the strained-Si thickness and the effective field dependent difference between electron and hole mobility enhancement factors of strained-SOI CMOS.
Starting Page	106
Ending Page	107
File Size	267476
Page Count	2
File Format	PDF
ISBN	078037312X
DOI	10.1109/VLSIT.2002.1015410
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Transistors Substrates Charge carrier processes Electron mobility CMOS technology Silicon germanium Germanium silicon alloys Buffer layers Delay effects
Content Type	Text
Resource Type	Article

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