NDLI: Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation

Content Provider	IEEE Xplore Digital Library
Author	Sauer, M. Kupferschmid, S. Czutro, A. Reddy, S. Becker, B.
Copyright Year	2012
Abstract	Test pattern generation for sequential circuits benefits from scanning strategies as these allow the justification of arbitrary circuit states. However, some of these states may be unreachable during normal operation. This results in non-functional operation which may lead to abnormal circuit behaviour and result in over-testing. In this work, we present a versatile approach that combines a highly adaptable SAT-based path-enumeration algorithm with a model-checking solver for invariant properties that relies on the theory of Craig interpolants to prove the unreachability of circuit states. The method enumerates a set of longest sensitisable paths and yields test sequences of minimal length able to sensitise the found paths starting from a given circuit state. We present detailed experimental results on the reach ability of sensitisable paths in ITC 99 circuits.
Starting Page	382
Ending Page	387
File Size	198391
Page Count	6
File Format	PDF
ISBN	9781467304382
ISSN	10639667
DOI	10.1109/VLSID.2012.101
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-01-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Delay Sequential circuits Circuit faults Integrated circuit modeling Interpolation Transfer functions mc sensitisable path longest path sequential circuit ATPG small delay fault justification reachability craig bmc
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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