NDLI: Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions

Content Provider	IEEE Xplore Digital Library
Author	Venkatraman, R. Pundoor, S. Koithyar, A. Rao, M. Rao, J.C.
Copyright Year	2009
Abstract	Design optimisation of large system-on-chip (SoC) designs presents significant challenges in terms of the number of care-abouts in today's chip design scenario. While optimisation approaches have focused on key aspects like design timing, power and routability, there are several critical aspects that do not get modelled by the abstraction approaches used in current solutions, resulting in local areas of potentially bad quality of results (QoR). The definition of design quality metrics for assessing various aspects of interest thus comes out as a key requirement in designs today. In this paper, we highlight the key challenges in the design of large, complex SoCs and propose some design metrics that identify problem areas for improvement. We highlight how conventional abstraction schemes tend to mask such problems when looking at design-level averaging for the relevant cost-functions. We present the results of these metrics and also show why not resolving some of these potential bottle-necks could lead to significant challenges in overall design closure.
Starting Page	525
Ending Page	530
File Size	354509
Page Count	6
File Format	PDF
ISBN	9780769535067
ISSN	10639667
DOI	10.1109/VLSI.Design.2009.52
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-01-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design optimization Quality assessment Algorithm design and analysis Chip scale packaging Timing Very large scale integration Instruments System-on-a-chip Power system modeling Phase estimation physical design Optimisation QoR assessment metrics
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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Optimization strategies to improve statistical timing

Future SoC design challenges and solutions

Hardware emulation of VLSI designs

Wire Optimization for Multimedia SoC and SiP Designs

Robust chip-level clock tree synthesis for SOC designs

Assessment of on-chip wire-length distribution models

SOC design challenges for embedded systems

Engineering changes in field modifiable architectures

Hierarchical physical design system

Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions

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Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions