NDLI: Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC

Content Provider	IEEE Xplore Digital Library
Author	Yotsuyanagi, H. Hashizume, M. Tsutsumi, T. Yamazaki, K. Aikyo, T. Higami, Y. Takahashi, H. Takamatsu, Y.
Copyright Year	2009
Abstract	Open faults are difficult to test since the voltage at the floating line is unpredicted and depends on the voltage at the adjacent lines. The modeling for open faults with considering adjacent lines has been proposed in [10]. In this work, the 90 nm IC is designed and fabricated to evaluate how the voltage at adjacent lines affect the defective line. The open fault macros with a transmission gate and with an intentional break are included in the IC. The nine lines are placed in parallel in three layers to observe the effect of the coupling capacitance when an open occurs. The benchmark circuits with the open fault macro are also included in the IC. The simulation and experimental results show that the relationship between the floating line and the adjacent lines. The experimental results are also compared with the open fault model that calculate the weighted sum of voltages at the adjacent lines.
Starting Page	91
Ending Page	96
File Size	607466
Page Count	6
File Format	PDF
ISBN	9780769535067
ISSN	10639667
DOI	10.1109/VLSI.Design.2009.60
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-01-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Voltage Capacitance Wires Logic testing Very large scale integration Signal design Design engineering Integrated circuit testing Coupling circuits coupling capacitance open fault defect-based testing adjacent lines
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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