NDLI: An 8-bit, 3.8GHz dynamic BiCMOS comparator for high-performance ADC

Content Provider	IEEE Xplore Digital Library
Author	Dey, S.K. Banerjee, S.
Copyright Year	2005
Description	Author affiliation: Dept. of E&ECE, Indian Inst. of Technol., Kharagpur, India (Dey, S.K.; Banerjee, S.)
Abstract	This paper deals with a monolithic dynamic voltage comparator with sampling speed up to 3.8GHz and a resolution of 8-bit. To improve the power-speed tradeoff, the front-end pre-amplifier is being designed with high f/sub T/ (80GHz) Si-SiGe heterojunction bipolar transistor (HBT) for higher speed while the dynamic latch along with the output buffer is implemented in 0.25/spl mu/m standard CMOS process to keep the power level low. To operate the CMOS latch at 3.8GHz sampling rate, a tailor made 3-/spl Phi/ clocking scheme is employed where the reset time of the latch falls up to 45ps in the reset mode. In the tracking mode, controlled decision transferring is done from pre-amplifier to the latch. At the latch output, a buffer with hysteresis is used to overcome the switching noise of latch and produce sharp, well defined digital data. The active power consumption by the core comparator is /spl sim/9mW and it takes a core area of /spl sim/0.017 mm/sup 2/.
File Size	346415
File Format	PDF
ISBN	0769525024
ISSN	10639667
DOI	10.1109/VLSID.2006.35
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	BiCMOS integrated circuits Latches Clocks Heterojunction bipolar transistors CMOS technology Sampling methods Voltage CMOS process Hysteresis Inverters
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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