NDLI: A comprehensive SoC design methodology for nanometer design challenges

Content Provider	IEEE Xplore Digital Library
Author	Kumar, R.R. Bedi, R. Rajagopal, R. Guruprasad, N. Subbarangaiah, K. Abbasi, T. Murthy, D.V.R. Prasad, P.K. Gude, D.R.
Copyright Year	2005
Description	Author affiliation: Magma Design Autom., Bangalore, India (Kumar, R.R.; Bedi, R.; Rajagopal, R.; Guruprasad, N.)
Abstract	Summary form only for tutorial. SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex design challenges in silicon which were not seen in higher geometries. This tutorial highlights nanometer chip design challenges and recommends a tool independent design flow which meets the current trends. Covered are ASIC synthesis concepts along with integrated design for testability flow. The focus here is on different approaches to address the convergence challenges during synthesis along with some of the key design optimizations and transformations which would directly impact quality of results (QoR) post P&R. Verification methodology is also discussed. New verification languages and structural tools for linting and code coverage, latest trends in functional verification from the methodology and technology perspective are covered. Also new verification methodology that identifies and provides definition of metrics for functional coverage is reviewed.
File Size	89931
File Format	PDF
ISBN	0769525024
ISSN	10639667
DOI	10.1109/VLSID.2006.7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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