NDLI: A framework for energy and transient power reduction during behavioral synthesis

Content Provider	IEEE Xplore Digital Library
Author	Mohanty, S.P. Ranganathan, N.
Copyright Year	2003
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA (Mohanty, S.P.; Ranganathan, N.)
Abstract	In deep submicron and nanometer designs for battery driven portable applications, the minimization of total energy, average power, peak power, and peak power differential are equally important. In this paper, we propose a framework for simultaneous reduction of these energy and transient power components during behavioral synthesis. A new parameter called "Cycle Power Profile Function" (CPF) is defined which captures the transient power characteristics as a weighted sum of mean cycle power and mean cycle differential power. Minimizing this parameter using multiple voltages and dynamic clocking results in reduction of both energy and transient power. Based on the above, a datapath scheduling algorithm called "CPF-Scheduler" is developed which attempts to minimize the CPF. Experimental results show that for two voltage levels, three operating frequencies, switching activity of 0.5 and power profiling factor of 0.5, the scheduler achieves (i) total energy reductions in the range of 27 - 53%, (ii) average power reductions in the range of 40 - 73% (iii) peak power reductions in the range of 58 - 78% and (iv) peak power differential reductions in the range of 60 - 97%. Further, the impact of switching, profiling factor and resource constraints on the power profile is studied in detail.
Sponsorship	VLSI Soc. India (VSI) Minstr. Commun. & Inf. Technol., Govern. India IEEE Circuits & Syst. Soc. ACM SIGDA NASSCOM
Starting Page	539
Ending Page	545
File Size	316546
Page Count	7
File Format	PDF
ISBN	0769518680
ISSN	10639667
DOI	10.1109/ICVD.2003.1183190
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-01-04
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Frequency Clocks Minimization Switching circuits Power system reliability Noise reduction Circuit noise Crosstalk Electromagnetic interference
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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