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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Pain, B. Hancock, B. Cunningham, T. Guang Yang Seshadri, S. Heynssens, J. Wrigley, C. |
| Copyright Year | 2003 |
| Description | Author affiliation: Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA (Pain, B.; Hancock, B.; Cunningham, T.; Guang Yang; Seshadri, S.; Heynssens, J.; Wrigley, C.) |
| Abstract | Due to substantial mixed analog-digital circuit integration in one chip, CMOS digital imager cannot be considered only as a photoelectric transducer. In this paper, we have identified timing and circuit layout considerations that are critical for implementing a digital CMOS camera-on-a-chip. An optimized binary-scaled tree-topology power routing has been shown to be critical for minimizing chip area and providing low spatial pattern noise. Imaging artifacts due to timing asymmetry have been quantified, and methods for elimination of the artifacts have been demonstrated. The impact of on-chip bias-generation and drive circuits on the on-chip ADC performance has been shown. New timing and circuit layout techniques have been presented for enabling random noise limited performance of a CMOS imager. |
| Sponsorship | VLSI Soc. India (VSI) Minstr. Commun. & Inf. Technol., Govern. India IEEE Circuits & Syst. Soc. ACM SIGDA NASSCOM |
| Starting Page | 395 |
| Ending Page | 400 |
| File Size | 717027 |
| Page Count | 6 |
| File Format | |
| ISBN | 0769518680 |
| ISSN | 10639667 |
| DOI | 10.1109/ICVD.2003.1183168 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-01-04 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Digital images System-on-a-chip CMOS digital integrated circuits Timing Pixel CMOS technology CMOS image sensors CMOS analog integrated circuits Circuit noise CMOS process |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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