NDLI: Formal system design based on the synchrony hypothesis, functional models, and skeletons

Content Provider	IEEE Xplore Digital Library
Author	Sander, I. Jantsch, A.
Copyright Year	1999
Description	Author affiliation: Dept. of Electron., R. Inst. of Technol., Stockholm, Sweden (Sander, I.)
Abstract	Formal approaches to HW and system design have not been generally adopted because designers often view the modelling concepts in these approaches as unsuitable for their problems. Moreover they are frequently on a too high abstraction level to allow for efficient synthesis with today's techniques. We address this problem with a modelling method, which is strictly formal and based on formal semantics, a pure functional language, and the synchrony hypothesis. But the use of skeletons in conjunction with a proper computational model allows to associate a direct hardware interpretation. In particular we use the synchrony hypothesis and a timed signal model to provide a high abstraction for communication at the system level. This facilitates efficient modelling and design space exploration at the functional level, because the designer is not concerned with complex communication mechanisms, and functionality can easily be moved from one block to another. To bridge the gap between an elegant and abstract functional model and the details of an implementation we use skeletons to encapsulate primitive structures, such as FSMs, buffers, computation units, etc. in a purely functional way.
Starting Page	318
Ending Page	323
File Size	50795
Page Count	6
File Format	PDF
ISBN	0769500137
ISSN	10639667
DOI	10.1109/ICVD.1999.745170
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-01-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Skeleton Computational modeling Hardware Bridges Product development Signal synthesis Signal design Message passing Computer industry Real time systems
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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