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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dave, B.P. |
| Copyright Year | 1999 |
| Description | Author affiliation: Bell Labs., Lucent Technol., Holmdel, NJ, USA (Dave, B.P.) |
| Abstract | Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-time reconfigurable hardware components such as field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). In this paper, we address the problem of hardware/ software co-synthesis of dynamically reconfigurable embedded systems. Our co-synthesis system, CRUSADE, takes as an input embedded system specifications in terms periodic acyclic task graphs with rate constraints and generates dynamically reconfigurable heterogeneous distributed hardware and software architecture meeting real-time constraints while minimizing the system hardware cost. We identify the group of tasks for dynamic reconfiguration of programmable devices and synthesize an efficient programming interface for reconfiguring reprogrammable devices. Real-time systems require that the execution time for tasks mapped to reprogrammable devices are managed effectively such that real-time deadlines are not exceeded. To address this, we propose a technique to effectively manage delay in reconfigurable devices. Our approach guarantees that the real-time task deadlines are always met. To the best of our knowledge, this is the first co-synthesis algorithm which targets dynamically reconfigurable embedded systems. We also show how our co-synthesis algorithm can be easily extended to consider fault-detection and fault-tolerance. Application of CRUSADE and its fault tolerance extension, CRUSADE-FT to several real-life large examples (up to 7400 tasks) from mobile communication network base station, video distribution router, a multi-media system, and synchronous optical network (SONET) and asynchronous transfer mode (ATM) based telecom systems shows that up to 56% system cost savings can be realized. |
| Starting Page | 97 |
| Ending Page | 104 |
| File Size | 63300 |
| Page Count | 8 |
| File Format | |
| ISBN | 0769500781 |
| DOI | 10.1109/DATE.1999.761103 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1999-03-09 |
| Publisher Place | Germany |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Embedded system Costs Real time systems Field programmable gate arrays Programmable logic arrays Dynamic programming SONET Asynchronous transfer mode Programmable logic devices |
| Content Type | Text |
| Resource Type | Article |
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