NDLI: Overcoming the serial logic simulation bottleneck in parallel fault simulation

Content Provider	IEEE Xplore Digital Library
Author	Rudmocl, E.M. Patel, J.H.
Copyright Year	1997
Description	Author affiliation: Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA (Rudmocl, E.M.)
Abstract	We propose a new approach to parallelizing fault simulation in which the test set is partitioned among the available processors. The approach can be used for any of the sequential circuit fault simulation algorithms commonly used, and it can be implemented on various different parallel architectures. This approach for the first time overcomes the limitations of serial logic simulation. In addition, the excessive redundant computations required in the traditional fault-partitioning approach are also considerably reduced. Significant improvements in speedup were observed as compared to previous approaches. An average speedup of 5.7 was obtained for test set partitioning over 10 processors for the benchmark circuits studied. Although pessimistic fault coverage may be reported in some cases, the proposed approach was found to be very accurate for the circuits studied.
Starting Page	495
Ending Page	501
File Size	801820
Page Count	7
File Format	PDF
ISBN	0818677554
ISSN	10639667
DOI	10.1109/ICVD.1997.568183
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-01-04
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit simulation Circuit testing Computational modeling Partitioning algorithms Logic testing Sequential circuits Concurrent computing Parallel architectures Benchmark testing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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