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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Suzuki, Daisuke Natsui, Masanori Ikeda, Shoji Hasegawa, Haruhiro Miura, Katsuya Hayakawa, Jun Endoh, Tetsuo Ohno, Hideo Hanyu, Takahiro |
| Copyright Year | 2009 |
| Description | Author affiliation: Laboratory for Brainware Systems, Research Institute of Electrical Communication, Tohoku Univ., Sendai, 980-8577, Japan (Suzuki, Daisuke; Natsui, Masanori; Hanyu, Takahiro) || Hitachi Advanced Research Laboratory, Tokyo, 185-8601, Japan (Hayakawa, Jun) || Center for Interdisciplinary Research, Tohoku University, Sendai, 980-8578, Japan (Endoh, Tetsuo) || Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku Univ., Sendai, 980-8577, Japan (Ikeda, Shoji; Hasegawa, Haruhiro; Miura, Katsuya; Ohno, Hideo) |
| Abstract | Series connection of metal-oxide semiconductor transistors and spin-injection-writable magneto-resistive junction devices based on logic-in-memory architecture realizes both programmable logic operation and nonvolatile storage function. A lookup table (LUT) circuit in field-programmable gate array fabricated by a 0.14µm magneto/semiconductor-hybrid process achieves area reduction by 2/3 compared to a conventional static random-access-memory-based one, and realizes complete standby power reduction. |
| Starting Page | 80 |
| Ending Page | 81 |
| File Size | 1820175 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781424433070 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-06-16 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | JSAP (Japan Society of Applied Physics) |
| Subject Keyword | Fabrication Magnetic circuits Magnetic semiconductors Field programmable gate arrays Programmable logic arrays Table lookup MOS devices Magnetic devices Logic devices Programmable logic devices |
| Content Type | Text |
| Resource Type | Article |
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