NDLI: A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective

Content Provider	IEEE Xplore Digital Library
Author	Zhou, Dajiang You, Zongyuan Zhu, Jiayi Kong, Ji Hong, Yu Chen, Xianmin He, Xuewen Xu, Chen Zhang, Hang Zhou, Jinjia Deng, Ning Liu, Peilin Goto, Satoshi
Copyright Year	2009
Description	Author affiliation: Graduate School of Information, Production and Systems, Waseda University, 2-7 Hibikino, 808-0135, Japan (Zhou, Dajiang; Zhou, Jinjia; Goto, Satoshi) \|\| Department of Electronic Engineering, Shanghai Jiao Tong University, China (You, Zongyuan; Zhu, Jiayi; Kong, Ji; Hong, Yu; Chen, Xianmin; He, Xuewen; Xu, Chen; Zhang, Hang; Deng, Ning; Liu, Peilin)
Abstract	In this paper, we present a video decoder chip for H.264/AVC high profile, MPEG-1/2 main profile and AVS Jprofile, which is capable of 60fps 1080p decoding at 200MHz. By applying a dedicated DRAM sub-system and a 2-D cache architecture, 50% of pins for DRAM connection and 36% of power consumption are saved, compared to state-of-the-art work in a system perspective. Meanwhile, 38% of gate count is reduced by applying resource sharing architectures between the 3 supported video formats.
Starting Page	262
Ending Page	263
File Size	1358748
Page Count	2
File Format	PDF
ISBN	9781424433070
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-16
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	JSAP (Japan Society of Applied Physics)
Subject Keyword	Decoding Costs Random access memory Pins Video sharing Resource management Packaging Bandwidth Displays Buffer storage
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Single-Chip Real-Time MPEG2 Video Decoder

A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

A SINGLE CHIP MPEG1 DECODER

A data-reuse scheme for avoiding unnecessary memory accesses in MPEG-4 ASP video decoder

A Low-Cost Multi-standard Audio Decoder Architecture Design

A full-HD 60fps AVS/H.264/VC-1/MPEG-2 video decoder for digital home applications

A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip

Design of Memory Sub-System in H.264/AVC Decoder

A single chip MPEG-1/CDROM decoder for video CD player applications

A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective

Similar Documents

A Single-Chip Real-Time MPEG2 Video Decoder

A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

A SINGLE CHIP MPEG1 DECODER

A data-reuse scheme for avoiding unnecessary memory accesses in MPEG-4 ASP video decoder

A Low-Cost Multi-standard Audio Decoder Architecture Design

A full-HD 60fps AVS/H.264/VC-1/MPEG-2 video decoder for digital home applications

A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip

Design of Memory Sub-System in H.264/AVC Decoder

A single chip MPEG-1/CDROM decoder for video CD player applications

A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective