NDLI: Developments in Dual Dielectric Charge-Storage (DDC) REPROM (REProgrammable Read Often Memories)

Content Provider	IEEE Xplore Digital Library
Author	Kahng, D.
Copyright Year	1976
Description	Author affiliation: Bell Laboratories, Murray Hill, New Jersey 07974 (Kahng, D.)
Abstract	There has been an increasing interest in recent months in the dual dielectric metal insulator semiconductor (MIS) cell as a nonvolatile semiconductor memory element. A true nonvolatile semiconductor memory could replace the omnipresent magnetic memory because associated with it one also expects fast access capability as well as interface compatibility with other semiconductor logic circuits. Key features in such a semiconductor memory cell, then are; true nonvolatility, high-speed access capability and ease of write-erase operations. The development of the dual-dielectric charge-storage (DDC) cells have followed two parallel paths, both enjoying a limited success yielding commercial products. The first centers around the concept of the floating gate, an artificially created metallic charge-storage site located at the dual dielectric interface. The second uses the naturally occurring interfacial states existing at the dual-dielectric interface as the charge storage sites, as in metal-nitride-oxide-semiconductor (MNOS) memory transistors. The advantages and disadvantages of these two approaches to the realization of DDC cells is reviewed briefly. And then the concept of the interfacial dopants, l the heart of this paper, emerges as a particularly beneficial compromise between these two concepts, resulting in an optimum DDC cell, with true nonvolatility, yet with undemanding write-eras conditions.
Starting Page	192
Ending Page	192
File Size	1040996
Page Count	1
File Format	PDF
ISSN	07350791
DOI	10.1109/IRPS.1976.362740
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1976-04-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nonvolatile memory Semiconductor memory Metal-insulator structures Dielectrics and electrical insulation Magnetic memory Logic circuits Heart Voltage
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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