NDLI: A design language for automatic synthesis of fault trees

Content Provider	IEEE Xplore Digital Library
Author	Kumar Vemuri, K. Dugan, J.B. Sullivan, K.J.
Copyright Year	1999
Description	Author affiliation: Hewlett Packard Co., Richardson, TX, USA (Kumar Vemuri, K.)
Abstract	The separation of digital system design and reliability analysis incurs unnecessary costs, delays and quality penalties. This paper introduces a graphical design language called RIDL (Reliability Information embedded Design Language) for modeling digital systems. In RIDL, redundancy and failure information is embedded within block diagram schematics, without significantly altering the physical block diagram models typically used by design engineers. A system schematic in RIDL has all of the information needed for reliability analysis without a need for additional textual descriptions. A dynamic fault tree model can be automatically synthesized from a RIDL system model. Designers can use the synthesized fault trees to obtain rough reliability analyses at an early conceptual design stage. To evaluate the potential of this approach, we have applied it to several example systems.
Starting Page	91
Ending Page	96
File Size	645217
Page Count	6
File Format	PDF
ISBN	0780351436
DOI	10.1109/RAMS.1999.744102
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-01-18
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault trees Reliability engineering Digital systems Information analysis Redundancy Delay Failure analysis Design engineering Costs Fault tolerant systems
Content Type	Text
Resource Type	Article

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