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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Annovi, A. Broccolo, G. Ciocci, A. Giannetti, P. Ligabue, F. Magalotti, D. Nappi, A. Dell'Orso, M. Dell'Orso, R. Palla, F. Pedreschi, E. Piendibene, M. Servoli, L. Taroni, S. Volpi, G. |
| Copyright Year | 2012 |
| Description | Author affiliation: University of Pisa, Italy (Dell'Orso, M.; Piendibene, M.) || Scuola Normale Superiore, Pisa, Italy (Broccolo, G.; Ligabue, F.) || University of Siena, Italy (Ciocci, A.) || INFN, Perugia, Italy (Magalotti, D.; Nappi, A.; Servoli, L.; Taroni, S.) || INFN LNF, Frascati, Italy (Annovi, A.; Volpi, G.) || INFN, Pisa, Italy (Giannetti, P.; Dell'Orso, R.; Palla, F.; Pedreschi, E.) |
| Abstract | The CDF Associative-Memory device (AM), proven technology developed for the Silicon-Vertex-Trigger at the CDF experiment, is one of the proposed solutions at the LHC for track reconstruction at level-1 in the HL-LHC upgrade, for very high-luminosity conditions (hundreds proton-proton collisions every 25 ns, at $5×10^{34}$ $cm^{−2}sec^{−1}).$ This luminosity requires a drastic revision of the existing trigger strategies. In the CMS experiment, one of the identified challenges for future upgrades is the capability of using already at L1 the tracker information to trigger events. Simulation studies show that this can be achieved by correlating hits on two closely spaced silicon strip sensors. This strategy requires massive computing power, to minimize the online execution time of complex tracking algorithms and the “combinatorial challenge”. The AM allows to compare the tracker information of each event to pre-calculated “expectations” (pattern matching) in a so short time that tracks can contribute to the trigger decision. One of the main challenges for the CMS tracker is the latency due to the tracker data distribution to the AM processors. A very parallelized readout architecture and a possible layout are discussed. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 1076888 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467310826 |
| e-ISBN | 9781467310840 |
| DOI | 10.1109/RTC.2012.6418193 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-06-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Roads Detectors Field programmable gate arrays Clocks Associative memory Program processors |
| Content Type | Text |
| Resource Type | Article |
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