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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Haomi Wang Kezhu Song Junfeng Yang Ping Cao Keli Zhang |
| Copyright Year | 2012 |
| Description | Author affiliation: Department of Modern Physics, University of Science and Technology of China, Chinese Academy of Science, Hefei, Anhui, 230026, China (Haomi Wang; Kezhu Song; Junfeng Yang; Ping Cao; Keli Zhang) |
| Abstract | Clock distribution system is an important part for Digital Coincidence Platform (DCP) which is used in 4πβ (LSC)-γ national benchmarks of the China Institute of Metrology. In this paper, the clock distribution was designed and produced by using the AD9524 chip and the external VCXO. The clock distribution board also generate sine wave signal for system test with the DDS chip AD9852 and trigger a synchronization signal to acquisition board through the PXI star trigger bus. The results show that the output to output skew of the clock is less than 50ps and the jitter of the clock signal is as low as 26ps. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 638864 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467310826 |
| e-ISBN | 9781467310840 |
| DOI | 10.1109/RTC.2012.6418157 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-06-09 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Synchronization Clocks Phase locked loops Field programmable gate arrays Jitter Software Hardware |
| Content Type | Text |
| Resource Type | Article |
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