NDLI: Challenges for ultra-wideband (UWB) CMOS integration

Content Provider	IEEE Xplore Digital Library
Author	Aiello, G.R.
Copyright Year	2003
Description	Author affiliation: Discrete Time Commun. Inc., San Diego, CA, USA (Aiello, G.R.)
Abstract	Various methods of utilizing the UWB spectrum have been developed to date, characterized by specific modulation schemes, such as pulse position, pulse amplitude or bi-phase modulation. A new method emerging today utilizes a multi-band approach, where information is encoded in multiple RF subbands at staggered time, each occupying 500 MHz bandwidth. A description of multi-band modulation schemes for UWB is included in the paper. The long term vision for UWB-based products is to enable personal devices with integrated wireless connectivity. This requires 110, 200 and 480 Mbps at 10 m, and reasonably low power consumption. UWB requires CMOS designs in order to achieve low power and low cost integration with other devices, and to fulfil the vision of integrated connectivity. One of the design challenges is the high operating frequencies (3.1-10.6 GHz), an additional challenge is that low Q systems are more sensitive to parasitics, especially in pads and wire bonds. Some UWB receiver architectures require good isolation among subbands. They also require quick switching between subbands at different frequencies. Example transmitter and receiver architectures are described in the paper.
Sponsorship	IEEE Microwave Theory & Tech. Soc. IEEE Electron. Device Soc. IEEE Solid States Circuits Soc
Starting Page	497
Ending Page	500
File Size	257574
Page Count	4
File Format	PDF
ISBN	0780376943
ISSN	15292517
DOI	10.1109/RFIC.2003.1213993
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-06-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Ultra wideband technology Bandwidth FCC Pulse modulation Amplitude modulation Costs Frequency Transceivers Space technology Phase locked loops
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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