NDLI: Design of a CMOS VCO with two tuning inputs applied for a wideband GFSK-modulated frequency synthesizer

Content Provider	IEEE Xplore Digital Library
Author	Peng, K.C. Huang, C.H. Li, C.J. Horng, T.S. Lee, S.F.
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. & Commun. Eng., Nat. Kaohsiung First Univ. of Sci. & Technol., Taiwan (Peng, K.C.)
Abstract	This paper describes the design considerations of a 2.4 GHz CMOS voltage-controlled oscillator (VCO) with two tuning inputs when used in a wideband GFSK-modulated frequency synthesizer based on a two-point delta-sigma modulation (TPDSM) architecture. One tuning input is provided mainly for the fractional-TV frequency synthesis, and the other one is for the direct GFSK modulation. In the VCO design, the tuning sensitivity for GFSK modulation is optimized including the effects of digital-to-analog converter (DAC). In addition, the size of spiral inductor in the LC tank is minimized without the cost of reducing quality (Q) factor. The implemented TPDSM-based GFSK-modulated frequency synthesizer can achieve a maximum data rate of up to 2.5 Mbps with an FSK error less than 1.4% and a phase-locked loop (PLL) settling time less than 110 /spl mu/s. The modulated frequency synthesizer with such good performances has promising application potential in a low-power solution for the enhanced data rate (EDR) Bluetooth transmitters.
Starting Page	443
Ending Page	446
File Size	1350639
Page Count	4
File Format	PDF
ISBN	0780394127
DOI	10.1109/RWS.2006.1615190
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage-controlled oscillators Tuning Wideband Frequency synthesizers Frequency shift keying Phase locked loops Delta-sigma modulation Digital modulation Design optimization Digital-analog conversion
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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