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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhiqiang Wan Jian Xiong Ji Lei Chen Chen |
| Copyright Year | 2015 |
| Description | Author affiliation: State Key Lab. of Adv. Electromagn. Eng. & Technol., Huazhong Univ. of Sci. & Technol., Wuhan, China (Zhiqiang Wan; Jian Xiong; Ji Lei; Chen Chen) |
| Abstract | The capacitor current feedback active damping is widely used in LCL converter. However, digital processor needs some time to calculate the output in digital control system which will result in sampling delay. The sampling delay will leads to system instability and unacceptable damping performance, especially in low switching frequency. This paper overcomes this issue by shifting the sampling instant close to the PWM updating instant. This approach can strengthen system stability and achieve sufficient active damping. Moreover, smaller sampling delay corresponds to larger damping ratio. The theoretical conclusions presented in this paper are verified by simulation and experiment. |
| Starting Page | 539 |
| Ending Page | 545 |
| File Size | 1217057 |
| Page Count | 7 |
| File Format | |
| ISBN | 9781479944026 |
| ISSN | 21645264 |
| DOI | 10.1109/PEDS.2015.7203467 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-06-09 |
| Publisher Place | Australia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delays Damping Switching frequency Capacitors Mathematical model Integrated circuits Pulse width modulation sampling delay LCL filter active damping capacitor current feedback |
| Content Type | Text |
| Resource Type | Article |
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