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Content Provider | IEEE Xplore Digital Library |
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Author | Ono, S. Saito, W. Takashita, M. Kurushima, S. Tokano, K. Yamaguchi, M. |
Copyright Year | 2007 |
Description | Author affiliation: Toshiba Corp., Kawasaki (Ono, S.; Saito, W.; Takashita, M.; Kurushima, S.; Tokano, K.; Yamaguchi, M.) |
Abstract | We report the experimental results detailed about the n-buffer layer (n-BAL: n-bottom assist layer) of 600 V-class semi-SJ MOSFET, and discuss about the design optimization by comparing the trade-off characteristics between the specific on-resistance $(R_{on}A)$ and the breakdown voltage $(V_{B}),$ the avalanche capability and the body diode characteristic for the first time. As design parameters, the thickness ratio $T_{BAL}-ratio$ and the doping concentration $N_{BAL}$ were varied in this work. As a result, the VB=750 V, the $R_{on}A=24.6$ $mOmegacm^{2},$ the maximum avalanche current density $J_{AP}=292$ $A/cm^{2}$ $(I_{AP}=7.6A,$ $E_{AS}=1.25$ $J/cm^{2}),$ and softness factor=0.277 were obtained with the structure of $T_{BAL}-ratio=27%$ and $N_{BAL}=1.0x10^{15}cm^{-3}.$ The demonstration results showed that NPT (non punch through)-type design (with high $T_{BAL}-ratio$ and high $N_{BAL})$ realized the larger avalanche capability and the softer reverse recovery characteristic compared with PT (punch through)-type design. |
Starting Page | 25 |
Ending Page | 28 |
File Size | 3291025 |
Page Count | 4 |
File Format | |
ISBN | 1424410959 |
DOI | 10.1109/ISPSD.2007.4294923 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2007-05-27 |
Publisher Place | South Korea |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | MOSFET circuits Doping Power MOSFET Voltage Power semiconductor devices Facsimile Design optimization Semiconductor diodes Current density Power supplies |
Content Type | Text |
Resource Type | Article |
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