NDLI: Affinity scheduling of unbalanced workloads

Content Provider	IEEE Xplore Digital Library
Author	Subramaniam, S. Eager, D.L.
Copyright Year	1994
Description	Author affiliation: Dept. of Comput. Sci., Saskatchewan Univ., Saskatoon, Sask., Canada (Subramaniam, S.; Eager, D.L.)
Abstract	Scheduling in a shared memory multiprocessor is often complicated by the fact that a unit of work may be processed more efficiently on one processor than on any other, due to factors such as the presence of required data in a local cache. The unit of work is said to have an "affinity" for the given processor, in such a case. The scheduling issue that has to be considered is the tradeoff between the goals of respecting processor affinities (so as to obtain improved efficiencies in execution) and of dynamically assigning each unit of work to whichever processor happens to be, at the time, least loaded (so as to obtain better load balance and decreased processor idle times). A specific context in which the above scheduling issue arises is that of shared memory multiprocessors with large per-processor caches or cached main memories. The shared-memory programming paradigm of such machines permits the dynamic scheduling of work. The data required by a unit of work may, however, often reside mostly in the cache of one particular processor, to which that unit of work thus has affinity. In this paper, two new "affinity scheduling" algorithms are proposed for a context in which the units of work have widely varying execution times. The two proposed algorithms are: (1) dynamic partitioned affinity scheduling and (2) wrapped partitioned affinity scheduling. An experimental study of these algorithms finds them to perform well in this context.
Starting Page	214
Ending Page	226
File Size	994346
Page Count	13
File Format	PDF
ISBN	0818666056
DOI	10.1109/SUPERC.1994.344281
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-11-14
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Processor scheduling Dynamic scheduling Operating systems Yarn Concurrent computing Dynamic programming Memory management Load management Engineering management Councils
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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