NDLI: Real-time GPS receiver implemented using Altera FPGA Board

Content Provider	IEEE Xplore Digital Library
Author	Yerabati, S. Zhen Hu Elkeelany, O.
Copyright Year	2010
Description	Author affiliation: Department of Electrical and Computer Engineering Tennessee Tech University (Yerabati, S.; Zhen Hu; Elkeelany, O.)
Abstract	Global Positioning System (GPS) is a space-based global navigation satellite system [1]. It provides time and location information to users anywhere on Earth [1]. Nowadays, GPS is very useful not only for military applications but also for civil applications. GPS receivers are placed in any embedded system to continuously calculate current time and location information. Hence, real-time synchronous systems can be designed. This paper presents the design challenges and implementation issues of real-time GPS receiver based on GPS Receiver Board and Altera DE2 FPGA Board. The functionalities of real time system is to receive the data packets from GPS Receiver board continuously and to display the time and location information using Altera DE2 Board in real time mode. The designed system also accepts set-up of desired time, so that synchronous actions can be made. These actions will be only done once the GPS time matches the set-up time. Finally, the field trial demonstrates the successful operation of the real-time GPS receiver system.
Starting Page	332
Ending Page	337
File Size	1869509
Page Count	6
File Format	PDF
ISBN	9781424458547
e-ISBN	9781424458530
DOI	10.1109/SECON.2010.5453859
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Global Positioning System Field programmable gate arrays Real time systems Timing Earth Application software Signal processing Liquid crystal displays Switches Military computing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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